GS9000 データシートの表示（PDF） - Gennum -> Semtech
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GS9000 Datasheet PDF : 8 Pages
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+5V
22µ
3 x 100n
SDIIN
SDIIN
SCIIN
SCIIN
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
+5V
100k
820p
**
12 13 18
1
VDD VDD VDD HSYNC 17
PD0
DECODER
5 SDI GS9000C
6 SDI
7 SCI
8 SCI
9 SS1
10 SS0
11 SSC
PDI 19
PD2 20
PD3 21
PD4 22
PD5 23
PD6 24
PD7 25
PD8 27
PD9 28
PCLK 16
SCE 14
VSS VSS VSS SWC SWF
2 4 26 15
3
** Locate the three 0.10µF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000C.
Chip capacitors are recommended.
HSYNC OUTPUT
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PARALLEL DATA BIT 9
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
10p
SYNC WARNING FLAG
13 x 425Ω
39k
+5V
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
Fig. 8 GS9000C Test Set-Up
With correctly synchronized serial data and clock connected
to the GS9000C, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can
also be fed through a suitable TTL to ECL converter to directly
drive parallel inputs to receiving equipment such as monitors
or digital to analog converters.
In operation, the HSYNC output from the GS9000C decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just
the time at which it toggles.
4ƒSC
DATA
STREAM
HSYNC
OUT
T
R
ACTIVE VIDEO
& H BLANKING
T
R
ACTIVE VIDEO
& H BLANKING
T
R
S
S
S
4:2:2
DATA
STREAM
EH
S
A BLNK A
V
V
ACTIVE
VIDEO
EH
S
A BLNK A
V
V
HSYNC
OUT
Fig. 9 Operation of HSYNC Output
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
522 - 49 - 01
PCLK
PDN
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
HSYNC
6
Fig. 10 Operation of HSYNC with Respect to PCLK
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