GL811S データシートの表示（PDF） - GENESYS LOGIC

部品番号

コンポーネント説明

メーカー

GL811S

USB2.0 to ATA / ATAPI Bridge Controller

GENESYS LOGIC 

GL811S USB2.0 to ATA/ATAPI Bridge Controller

- Signal transition (asserted or negated)

- Data transition (asserted or negated)

- Data valid

- Undefined but not necessarily released

- Asserted, negated or released

- Released

- The “other” condition if a signal is shown with no change

All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown

towards the bottom of the page relative to the asserted condition.

The interface uses a mixture of negative and positive signals for control and data. The terms asserted and

negated are used for consistency and are independent of electrical characteristics.

In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following

illustrates the representation of a signal named Test going from negated to asserted and back to negated, based

on the polarity of the signal.

©2007 Genesys Logic Inc. - All rights reserved.

Page 20

Share Link: