HT1647 データシートの表示（PDF） - Holtek Semiconductor
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一致するリスト
HT1647 Datasheet PDF : 17 Pages
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HT1647
Pad No.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
X
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1690.00
-1690.00
-1690.00
-1430.20
-1294.80
-1149.50
-1013.90
-872.80
-738.30
-600.10
-465.60
Y
-149.00
-277.00
-408.80
-536.80
-668.60
-796.60
-928.80
-1056.80
-1189.00
-1375.40
-1515.40
-1651.00
-1599.90
-1599.90
-1599.90
-1599.90
-1600.00
-1600.00
-1600.00
-1600.00
Pad No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
X
1522.60
1654.40
1782.40
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
Y
-1712.30
-1712.30
-1712.30
-1411.10
-1283.10
-1151.30
-1023.30
-891.50
-763.50
-631.70
-503.70
-371.90
-243.90
-112.10
15.90
147.70
275.70
407.50
535.50
667.30
Pad No.
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
X
823.50
691.70
563.70
431.90
303.90
172.10
44.10
-87.70
-215.70
-347.50
-475.50
-607.30
-735.30
-867.10
-995.10
-1126.90
-1254.90
-1386.70
-1514.70
-1646.50
Y
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
Pad Description
Pad No.
Pad Name
23
CS
24
RD
25
26~29
30
31
WR
DB0~DB3
VSS
OSCI
32
OSCO
33
34
35
36, 37
38~41
42~57
58~99,
1~22
VDD
VLCD
IRQ
BZ, BZ
T1~T4
COM0~COM15
SEG0~SEG63
I/O
Description
Chip selection input with pull-high resistor. When the CS is logic high, the
data and command read from or write to the HT1647 are disabled. The serial
I interface circuit is also reset. But if the CS is at a logic low level and is input to
the CS pad, the data and command transmission between the host control-
ler and the HT1647 are all enabled.
READ clock input with pull-high resistor. Data in the RAM of the HT1647 are
I
clocked out on the rising edge of the RD signal. The clocked out data will ap-
pear on the data line. The host controller can use the next falling edge to
latch the clocked out data.
I
WRITE clock input with pull-high resistor. Data on the DATA line are latched
into the HT1647 on the rising edge of the WR signal.
I/O Parallel data input/output with a pull-high resistor
¾ Negative power supply for logic circuit, ground
I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
O if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left
open.
¾ Positive power supply for logic circuit
I Power supply for LCD driver circuit
O Time base or Watchdog Timer overflow flag, NMOS open drain output.
O 2kHz or 4kHz frequency output pair (tristate output buffer)
I Not connected
O LCD common outputs
O LCD segment outputs
Rev. 1.30
4
November 10, 2005
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