MC54F283J データシートの表示（PDF） - Motorola => Freescale
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MC54F283J Datasheet PDF : 5 Pages
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4-BIT BINARY FULL ADDER
(With Fast Carry)
The MC54/74F283 high-speed 4-bit binary full adder with internal carry
lookahead, accepts two 4-bit binary words (A0–A3, B0–B3) and a Carry input
(C0). It generates the binary Sum outputs (S0–S3) and the Carry output (C4)
from the most significant bit. The F283 will operate with either active-HIGH or
active-LOW operands (positive or negative logic).
MC54/74F283
4-BIT BINARY FULL ADDER
(With Fast Carry)
FAST™ SCHOTTKY TTL
FUNCTIONAL DESCRIPTION
The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C0.
The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs.
The binary weight of the various inputs and outputs is indicated by the sub-
script numbers, representing powers of two.
20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3)
= S0 + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation.Thus C0,
A0, B0 can be arbitrarily assigned to pins 5, 6 and 7. Due to the symmetry of
the binary add function, the F283 can be used either with all inputs and outputs
active HIGH (positive logic) or with all inputs and outputs active LOW (nega-
tive logic). See Figure A. Note that if C0 is not used it must be tied LOW for
active-HIGH logic or tied HIGH for active-LOW logic.
Due to pin limitations, the intermediate carries of the F283 are not brought
out for use as inputs or outputs. However, other means can be used to effec-
tively insert a carry into, or bring a carry out from, an intermediate stage. Fig-
ure B shows how to make a 3-bit adder. Tying the operand inputs of the fourth
adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from
the third adder. Using somewhat the same principle, Figure C shows a way
of dividing the F283 into a 2-bit and a 1-bit adder. The third stage adder (A2,
B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth
stage (via A2 and B2) and bringing out the carry from the second stage on S2.
Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do
not influence S2. Similarly, when A2 and B2 are the same the carry into the third
stage does not influence the carry out of the third stage. Figure D shows a
method of implementing a 5-input encoder, where the inputs are equally
weighted. The outputs S0, S1 and S2 present a binary number equal to the
number of inputs I1–I5 that are true. Figure E shows one method of implement-
ing a 5-input majority gate. When three or more of the inputs I1–I5 are true, the
output M5 is true.
CONNECTION DIAGRAM
VCC B2 A2 S2 A3 B3 S3 C4
16 15 14 13 12 11 10 9
1 2 3 4 56 78
S1 B1 A1 S0 A0 B0 C0 GND
FAST AND LS TTL DATA
4-146
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
7
C0
4
S0
A0 5
B0 6
1
S1
A1 3
B1 2
13
S2
A2 14
B2 15
10
S3
A3 12
B3 11
C4
VCC = PIN 16
9
GND = PIN 8
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