MD56V62320 データシートの表示（PDF） - Oki Electric Industry

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MD56V62320

4-Bank x 524,288-Word x 32-Bit SYNCHRONOUS DYNAMIC RAM

Oki Electric Industry 

¡ Semiconductor

MD56V62320

PIN DESCRIPTION

CLK

CS

CKE

Address

BA0, BA1

RAS

CAS

WE

Fetches all inputs at the "H" edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0 - 3.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Row & column multiplexed.

Row address: RA0 - RA10

Column address: CA0 - CA7

Bank Access pins. These pins are dedicated to select one of 4 banks.

Functionality depends on the combination. For details, see the function truth table.

DQM0 - 3

DQi

DQM0 controls DQ1 - 8. DQM1 controls DQ9 - 16.

DQM2 controls DQ17 - 24. DQM3 controls DQ25 - 32.

Data inputs/outputs are multiplexed on the same pin.

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