QL3004 データシートの表示（PDF） - QuickLogic Corporation

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QL3004

Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

pASIC 3 FPGA Family Data Sheet Rev. D

Power-Up Sequencing

Figure 5: Power-Up Requirements

VCCIO

VCC

(VCCIO -VCC)MAX

VCC

400 us

Time

When powering up a device, the VCC/VCCIO rails must take 400 µs or longer to reach the maximum value

(refer to Figure 5).

NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 µs can cause the device to behave

improperly.

For users with a limited power budget, keep (VCCIO -VCC)MAX ≤ 500 mV when ramping up the power supply.

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