DS21372 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21372

3.3V Bit Error Rate Tester (BERT)

Dallas Semiconductor -> Maxim Integrated 

DS21372

1.5 POWER-UP SEQUENCE

On power-up, the registers in the DS21372 will be in a random state. The user must program all the

internal registers to a known state before proper operation can be insured.

DS21372 FUNCTIONAL BLOCK DIAGRAM Figure 1

DS21372 PATTERN GENERATION BLOCK DIAGRAM Figure 2

NOTES:

1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern.

2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.

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