DS21348 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21348 Datasheet PDF : 73 Pages
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MCLK SELECTION Table 6-1
MCLK
2.048MHz
2.048MHz
1.544MHz
JAMUX
(CCR1.3)
0
1
0
ETS
(CCR1.7)
0
1
1
DS21348/Q348
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)
P25S
n/a
SCLD
CLDS
RHBE
THBE
TCES
(LSB)
RCES
SYMBOL
POSITION DESCRIPTION
P25S
-
SCLD
CLDS
RHBE
THBE
TCES
RCES
CCR2.7
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
CCR2.1
CCR2.0
Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5ms
Not Assigned. Should be set to zero when written to.
Short Circuit Limit Disable (ETS = 0). Controls the 50 mA
(rms) current limiter.
0 = enable 50 mA current limiter
1 = disable 50 mA current limiter
Custom Line Driver Select. Setting this bit to a one will
redefine the operation of the transmit line driver. When this bit
is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the
device will generate a square wave at the TTIP and TRING
outputs instead of a normal waveform. When this bit is set to a
one and CCR4.5 = CCR4.6 = CCR4.7 ¹ 0, then the device will
force TTIP and TRING outputs to become open drain drivers
instead of their normal push-pull operation. This bit should be
set to zero for normal operation of the device. Contact the
factory for more details on how to use this bit.
Receive HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit Clock Edge Select. Selects which TCLK edge to
sample TPOS and TNEG.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
Receive Clock Edge Select. Selects which RCLK edge to
update RPOS and RNEG.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
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