DS2143Q データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

部品番号

コンポーネント説明

一致するリスト

DS2143Q

E1 Controller

Dallas Semiconductor -> Maxim Integrated 

PIN DESCRIPTION Table 1

DS2143/DS2143Q

PIN SYMBOL TYPE

DESCRIPTION

1

TCLK

I Transmit Clock. 2.048 MHz primary clock. A clock must be

applied at the TCLK pin for the parallel port to operate properly.

2

TSER

I Transmit Serial Data. Transmit NRZ serial data, sampled on the

falling edge of TCLK.

3

TCHCLK

O Transmit Channel Clock. 256 kHz clock which pulses high during

the LSB of each channel. Useful for parallel-to-serial conversion of

channel data. See Section 13 for timing details.

4

TPOS

O Transmit Bipolar Data. Updated on rising edge of TCLK. For

5

TNEG

optical links, can be programmed to output NRZ data.

6-13 AD0-AD7 I/O Address/Data Bus. An 8-bit multiplexed address/data bus.

14

BTS

I Bus Type Select. Strap high to select Motorola bus timing; strap

low to select Intel bus timing. This pin controls the function of

RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins

assume the function listed in parentheses ().

15

RD (DS)

I Read Input (Data Strobe).

16

CS

I Chip Select. Must be low to read or write the port.

17

ALE(AS)

I Address Latch Enable (Address Strobe). A positive-going edge

serves to demultiplex the bus.

18

WR (R/ W )

I Write Input (Read/Write).

19

RLINK

O Receive Link Data. Outputs Sa bits. See Section 13 for timing

details.

20

VSS

21

RLCLK

- Signal Ground. 0.0 volts.

O Receive Link Clock. 4 kHz to 20 kHz demand clock for the

RLINK output. Controlled by RCR2. See Section 13 for timing

details.

22

RCLK

I Receive Clock. 2.048 MHz primary clock. A clock must be applied

at the RCLK pin for the parallel port to operate properly.

23 RCHCLK

O Receive Channel Clock. 256 kHz clock which pulses high during

the LSB of each channel. Useful for serial to parallel conversion of

channel data. See Section 13 for timing details.

24

RSER

O Receive Serial Data. Received NRZ serial data, updated on rising

edges of RCLK.

25

RSYNC

I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this

pin which identifies either frame (RCR1.6=0) or multiframe

boundaries (RCR1.6=1). If the elastic store is enabled via the

RCR2.1, then this pin can be enabled to be an input via RCR1.5 at

which a frame boundary pulse is applied. See Section 13 for timing

details.

26

RPOS

I Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.

27

RNEG

Tie together to receive NRZ data and disable BPV monitoring

circuitry.

28

SYSCLK

I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when

the elastic store function is enabled via the RCR2.1. Should be tied

low in applications that do not use the elastic store.

4 of 44

Share Link: