DS1677(2000) データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
部品番号
コンポーネント説明
一致するリスト
DS1677 Datasheet PDF : 17 Pages
| |||
DS1677
MICROPROCESSOR MONITOR
The DS1677 monitors three vital conditions for a micro-processor: power supply, software execution, and
external override.
First, a precision temperature–compensated reference and comparator circuit monitors the status of VCC.
When an out–of–tolerance condition occurs, an internal power–fail signal is generated which forces the
RST pin to the active state thus warning a processor–based system of impending power failure. When
VCC returns to an in–tolerance condition upon power–up, the reset signal is kept in the active state for
250 ms (typical) to allow the power supply and microprocessor to stabilize. Note however that if the
EOSC bit is set to a logic 1 (to disable the oscillator during battery back–up mode), the RST signal will be
kept in an active state for 250 ms plus the start–up time of the oscillator.
The second monitoring function is push-button reset control. The DS1677 provides for a push–button
switch to be connected to the RST output pin. When the DS1677 is not in a reset cycle, it continuously
monitors the RST signal for a low going edge. If an edge is detected, the DS1677 will debounce the
switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1677 will
continue to monitor the RST line. If the line is still low, the DS1677 will continue to monitor the line
looking for a rising edge. Upon detecting release, the DS1677 will force the RST line low and hold it
low for 250 ms.
The third microprocessor monitoring function provided by the DS1677 is a watchdog timer. The
watchdog timer function forces RST to the active state when the ST input is not stimulated within the
predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 4). If TD0 and TD1 are both set to
zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set
time period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with
1000 ms time delay. If a high–to–low transition occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time–out, then
the RST signal is driven to the active state for 250 ms (typical). The ST input can be derived from
microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog
timer does not time–out, a high–to–low transition must occur at or less than the minimum period.
WATCHDOG TIME–OUT CONTROL Figure 4
WATCHDOG REGISTER
BIT 7
BIT 6
BIT 5
0
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
TD1
BIT 0
TD0
WATCHDOG REGISTER
TD1
TD0
0
0
0
1
1
0
1
1
WATCHDOG TIME-OUT
WATCHDOG DISABLED
250 ms
500 ms
1000 ms
8 of 17
Share Link: 