DS1110LE-150 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1110LE-150

3V 10-Tap Silicon Delay Line

Dallas Semiconductor -> Maxim Integrated 

3V 10-Tap Silicon Delay Line

Terminology

Period: The time elapsed between the leading edge of

the first pulse and the leading edge of the following pulse.

tWI (Pulse Width): The elapsed time on the pulse

between the 1.5V point on the leading edge and the

1.5V point on the trailing edge, or the 1.5V point on the

trailing edge and the 1.5V point on the leading edge.

tRISE (Input Rise Time): The elapsed time between the

20% and the 80% point on the leading edge of the

input pulse.

tFALL (Input Fall Time): The elapsed time between the

80% and the 20% point on the trailing edge of the input

pulse.

tPLH (Time Delay Rising): The elapsed time between

the 1.5V point on the leading edge of the input pulse

and the 1.5V point on the leading edge of any tap out-

put pulse.

tPHL (Time Delay, Falling): The elapsed time between

the 1.5V point on the trailing edge of the input pulse

and the 1.5V point on the trailing edge of any tap out-

put pulse.

Test Setup Description

Figure 3 illustrates the hardware configuration used for

measuring the timing parameters on the DS1110L. A

precision pulse generator under software control pro-

duces the input waveform. Time delays are measured

by a time interval counter (20ps resolution) connected

PULSE

GENERATOR

Z0 = 50Ω

START

TIME

INTERVAL

COUNTER

STOP

VHF SWITCH

CONTROL UNIT

Figure 3. Test Circuit

DEVICE UNDER TEST

6 ______________________________________________________________________

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