DS1110LE-125 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS1110LE-125 Datasheet PDF : 7 Pages
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3V 10-Tap Silicon Delay Line
Detailed Description
The DS1110L 10-tap delay line is a 3V version of
the DS1110. It has 10 equally spaced taps providing
delays from 10ns to 500ns. The device is offered in a
standard 14-pin TSSOP. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever is
greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L repro-
duces the input-logic state at the tap 10 output after a
fixed delay as specified by the dash-number suffix of the
part number (Table 1). The DS1110L produces both lead-
ing- and trailing-edge delays with equal precision. Each
tap is capable of driving up to 10 74LS-type loads. Dallas
Semiconductor can customize standard products to meet
specific needs. Figure 1 is the DS1110_L logic diagram
and Figure 2 shows the timing diagram for the silicon
delay line.
Table 1. Part Number by Delay (tPHL, tPLH)
PART
DS1110LE-100
DS1110LE-125
DS1110LE-150
DS1110LE-175
DS1110LE-200
DS1110LE-250
DS1110LE-300
DS1110LE-350
DS1110LE-400
DS1110LE-450
DS1110LE-500
TOTAL DELAY (ns)
100
125
150
175
200
250
300
350
400
450
500
DELAY/TAP (ns)
10
12.5
15
17.5
20
25
30
35
40
45
50
TAP1
TAP2
TAP9
TAP10
IN
Figure 1. Logic Diagram
10%
10%
10%
10%
PERIOD
tRISE
tFALL
VIH
2.4V
2.4V
1.5V
1.5V
1.5V
0.6V
IN VIL
0.6V
tWI
tWI
tPLH
tPLH
1.5V
1.5V
OUT
Figure 2. Timing Diagram: Silicon Delay Line
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