DS1110LE-100 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1110LE-100

3V 10-Tap Silicon Delay Line

Dallas Semiconductor -> Maxim Integrated 

3V 10-Tap Silicon Delay Line

CAPACITANCE

(TA = +25°C.)

PARAMETER

Input Capacitance

SYMBOL

CIN

CONDITIONS

MIN TYP MAX UNITS

5

10

pF

Note 1: All voltages are referenced to ground.

Note 2: Measured with outputs open.

Note 3: Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and trailing edges.

Note 4: Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to

3.6V range.

Note 5: Intermediate delay values are available on a custom basis.

Note 6: See Test Conditions section.

Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other

taps also slow down; tap 3 can never be faster than tap 2.

Note 8: Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.).

Note 9: For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.

(VCC = 3.3V, TA = +25°C, unless otherwise noted.)

Typical Operating Characteristics

0.10

0.05

0

-0.05

-0.10

-0.15

-0.20

-0.25

-0.30

-0.35

2.7

DELAY CHANGE (%)

vs. VCC DS1110L-500

RAISING EDGE

FALLING EDGE

3.0

3.3

3.6

VCC (V)

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

2.7

DELAY CHANGE (%)

vs. VCC DS1110L-250

RAISING EDGE

FALLING EDGE

3.0

3.3

3.6

VCC (V)

CHANGE IN DELAY (%) vs. TEMPERATURE

DS1110L-500

6

5

4

3

2

1

0

-1

RISING EDGE

FALLING EDGE

-2

-3

-4

-5

-40 -15

10

35

60

85

TEMPERATURE (°C)

CHANGE IN DELAY (%) vs. TEMPERATURE

DS1110L-250

4

3

2

1

0 RISING EDGE

FALLING EDGE

-1

-2

-3

-40 -15

10

35

60

85

TEMPERATURE (°C)

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