DM9003 データシートの表示（PDF） - Davicom Semiconductor, Inc.

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DM9003

10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface

Davicom Semiconductor, Inc. 

DM9003

2-port Switch with Processor Interface

1. GENERAL DESCRIPTION

The DM9003 is a fully integrated, high-

performance, and cost-effective Fast Ethernet switch

controller with one general processor bus interface,

two port 10M/100Mbps PHYs.

The general processor bus connects directly to

internal host MAC with 8-bit or 16-bit data to access

internal memory. The host MAC has the similar functions as

other 10M/100Mbps MAC do. This makes the DM9003 to

act as an extended three port switch and to shorten the

latency from processor port to destination port.

The internal memory of the DM9003 supports up

to 1K uni-cast MAC address table, and serves two

ports’ and processor port’s transmit and receive

buffers. For efficient memory usage algorithm, total

48KB memory is shared with two ports and processor

port by link list data structure.

Each port of the DM9003 provides four priorities

transmit queues, which can be defined as port-based,

802.1p VLAN, or IP packet ToS field, to fit the various

bandwidth and latency requirement of data, voice,

and video applications. Each port also supports

ingress and/or egress rate control to provide proper

bandwidth. And up to 16 groups of 802.1Q VLAN with

Tag/Un-tag functions are supported to provide

efficient packet forwarding.

The TCP/UDP/IPv4 checksum generation and

checking functions are also provided by processor

port to offload the processor’s computing load. In

addition to the packet transmit and receive functions,

the processor port also provides various registers to

control and get status of the DM9003’s operation.

Each port, including the processor port, provides the

MIB counters, loop-back capability and the memory

Build-in Self Test (BIST) for system and board level

diagnostic.

The integrated two ports PHY are compliant with

IEEE 802.3u standards and supports HP Auto-MDIX

capabilities for twisted-pair cable transmit/receive

direction automatic switching.

2. BLOCK DIAGRAM

Port 0

MDI / MDIX

Port 1

MDI / MDIX

10 / 100 M

PHY

10/ 100 M

MAC

10/ 100 M

PHY

10/ 100 M

MAC

Switch Fabric

Switch Engine

Embedded

Memory

Memory

BIST

Switch

Controller

Memory

Management

8 / 16 bit

Processor

Bus

Processor

Interface

Host

MAC

Control

Registers

MIB

Counters

EEPROM

Interface

EEPROM

Preliminary datasheet

9

DM9003-15-DS-P05

April 9, 2009

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