NT7501 データシートの表示（PDF） - Novatek Microelectronics

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NT7501

33 X 100 RAM-Map LCD Controller/Driver

Novatek Microelectronics 

NT7501

5. Read Status

A0 E R
W D7

D6

D5

D4 D3 D2 D1 D0

RD WR

0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0

Busy:

ADC:

ON/OFF:

RESET:

When high, the NT7501 is busy due to either internal operation or being reset. Any command is rejected until

BUSY goes low. The busy check is not required if enough time is provided for each cycle.

Indicates the relationship between RAM column address and segment drivers. When low, the display is

reversed and the column address “100-n” corresponds to segment driver n. When high, the display is normal

and column address corresponds to segment driver n.

Indicates whether the display is on or off. When it goes low the display turns on. When it goes high, the

display turns off. This is the opposite of Display ON/OFF command

Indicates that initialization is in progress due to RES signal or by reset command. When low, the display is

on. When high, the chip is being reset.

6. Write Display Data

Write 8-bit data in the display RAM. As the column address is incremented by 1 automatically after each writing, the

microprocessor can continue to write data of multiple words.

A0 E R
W D7 D6 D5 D4 D3 D2 D1 D0

RD WR

11 0

Write data

7. Read Display Data

Reads 8-bit data from the display RAM area specified by the column address and page address. As the column address is

incremented by 1 automatically after each reading, the microprocessor can continue to read data of multiple words. A

single dummy reading is required immediately after the column address setup. Refer to the display RAM section of

FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

10 1

Read data

8. ADC Select

Changes the relationship between the RAM column address and the segment driver. The order of the segment driver

output pads can be reversed by the software. This allows flexible IC layout during the LCD module assembly. For details,

refer to the column address section of Figure4. When display data is written or read, the column address is incremented by

1 as shown in Figure4.

A0 E R
W D7 D6 D5 D4 D3 D2 D1 D0

RD WR

0 1 0 1010000D

When D is low, the right rotation (normal direction)

When D is high, the left rotation (reverse direction)

9. Normal/ Reverse Display

Reverses the Display ON/OFF status without rewriting the contents of the display data RAM.

A0 E R
W D7 D6 D5 D4 D3 D2 D1 D0

RD WR

0 1 0 1010011D

When D is low, the RAM data is high, being LCD ON potential (normal display)

When D is high, the RAM data is low, being LCD ON potential (reverse display)

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