CY7C68023-56LTXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C68023-56LTXC Datasheet PDF : 10 Pages
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CY7C68023/CY7C68024
Configuration Data
Certain features in the NX2LP can be configured by the designer to disable unneeded features, and to comply with the USB 2.0
specification’s descriptor requirements for mass storage devices. Table 1 lists the variable configuration data and the default values
that are stored in internal ROM space. The default ROM values are returned by an unprogrammed NX2LP device.
Table 1. Variable Configuration Data And Default ROM Values
Configuration Data
Vendor ID
Product ID
Serial Number
Manufacturer String
Product String
Description
USB Vendor ID (Assigned by USB-IF)
USB Product ID (Assigned by designer)
USB serial number
Manufacturer string in USB descriptors
Product string in USB descriptors
Default ROM Value
0x04B4 (Cypress)
0x6813
N/A
N/A
N/A
Enable Write Protection Enables write protection capability
Enabled
SCSI Device Name String shown in the device manager properties
N/A
Design Notes For The Quad Flat No Lead
(QFN) Package
The NX2LP comes in a 56-pin QFN package, which utilizes a
metal pad on the bottom to aid in heat dissipation. The low-power
operation of the NX2LP makes the thermal pad on the bottom of
the QFN package unnecessary. Because of this, PCB layout may
utilize the space under the NX2LP for routing signals as needed,
provided that any traces or vias under the thermal pad are
covered by solder mask or other material to prevent shorting.
Standard PCB layout recommendations for USB devices still
apply.
For further information on this package design, please refer to
the application note from AMKOR titled “Surface Mount
Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.”
This application note provides detailed information on board
mounting guidelines, soldering flow, rework process, etc.
PCB Layout Recommendations
The following recommendations should be followed to ensure
reliable High-speed USB performance operation.
■ A four-layer impedance controlled board is recommended to
ensure best signal quality.
■ Specify impedance targets (ask your board vendor what they
can achieve).
■ Maintain trace widths and trace spacing to control impedance.
■ Minimize stubs on DPLUS and DMINUS to avoid reflected
signals.
■ Place any connections between the USB connector shell and
signal ground near the USB connector.
■ Use bypass/flyback caps on VBUS, placed near connector.
■ Keep DPLUS and DMINUS trace lengths to within 2 mm of
each other in length, with preferred length of 20–30 mm.
■ Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
■ Place no vias on the DPLUS or DMINUS trace routing.
■ Isolate the DPLUS and DMINUS traces from all other signal
traces (use >10 mm. spacing for best signal quality).
Source for recommendations:
■ EZ-USB FX2 PCB Design
www.cypress.com/?docID=4696.
Recommendations,
■ High-speed USB Platform Design Guidelines,
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Document #: 38-08055 Rev. *E
Page 6 of 10
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