CY7C4292-10 データシートの表示（PDF） - Cypress Semiconductor

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CY7C4292-10

64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion

Cypress Semiconductor 

CY7C4282

CY7C4292

DATA IN (D) 18 9

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

PROGRAMMABLE(PAE)

HALF FULL FLAG (HF)

RESET (RS)

CY7C4282/92

FULL FLAG (FF)

FF

EF

9

RESET (RS)

9

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAF)

CY7C4282/92

EMPTY FLAG (EF)

FF

EF

9 DATA OUT (Q) 18

FIRST LOAD (FL)

EXPANSION IN (XI)

FIRST LOAD (FL)

EXPANSION IN (XI)

Figure 2. Block Diagram of 64K × 9/128K × 9 1M Deep Sync FIFO Memory Used

in a Width Expansion Configuration

Document #: 38-06009 Rev. *B

Page 6 of 16

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