CY7C1485V25 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1485V25 Datasheet PDF : 26 Pages
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CY7C1484V25
CY7C1485V25
Pin Definitions (continued)
Pin Name
IO
Description
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode Pin has an internal pull up.
TDO
JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous feature is not used, this pin should be disconnected. This pin is not available on TQFP
packages.
TDI
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Input
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
Synchronous TQFP packages.
TMS
JTAG Serial
Input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
NC
JTAG Clock
–
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die
NC(144M,
288M,
576M, 1G)
–
These pins are not connected. They will be used for expansion to the 144M, 288M, 576M
and 1G densities.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1484V25/CY7C1485V25 supports secondary
cache in systems using either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486™ processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the ADSP or
ADSC. The ADV input controls address advancement through
the burst sequence. A two-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. GW overrides all
byte write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state; its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
OE signal controls the outputs. Consecutive single read cycles
are supported.
The CY7C1484V25/CY7C1485V25 is a double cycle deselect
part. After the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output tri-states
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses need two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the BWE and BWX signals control the write operation.
The CY7C1484V25/CY7C1485V25 provides byte write
capability that is described in the “Truth Table for Read/Write”
on page 9. Asserting BWE with the selected Byte Write input
will selectively write to only the desired bytes. Bytes not
selected during a byte write operation remain unaltered. A
synchronous self timed write mechanism is provided to
simplify the write operations.
Because the CY7C1484V25/CY7C1485V25 is a common IO
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so tri-states the
output drivers. As a safety precaution, DQ are automatically
Document #: 38-05286 Rev. *H
Page 6 of 26
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