CY7C1339F データシートの表示（PDF） - Cypress Semiconductor
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CY7C1339F Datasheet PDF : 17 Pages
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CY7C1339F
Burst Sequences
The CY7C1339F provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
Min.
Max.
Unit
ZZ > VDD – 0.2V
40
mA
ZZ > VDD – 0.2V
2tCYC
ns
ZZ < 0.2V
2tCYC
ns
This parameter is sampled
2tCYC
ns
This parameter is sampled
0
ns
Truth Table[ 2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power-down None
H X XL X
L
X
X
X L-H three-state
Deselect Cycle, Power-down None
L L XL L
X
X
X
X L-H three-state
Deselect Cycle, Power-down None
L X HL L
X
X
X
X L-H three-state
Deselect Cycle, Power-down None
L L XL H
L
X
X
X L-H three-state
Deselect Cycle, Power-down None
L X HL H
L
X
X
X L-H three-state
Snooze Mode, Power-down None
X X XH X
X
X
X
X X three-state
READ Cycle, Begin Burst
External L H L L L
X
X
X
L L-H
Q
READ Cycle, Begin Burst
External L H L L L
X
X
X
H L-H three-state
WRITE Cycle, Begin Burst External L H L L H
L
X
L
X L-H
D
READ Cycle, Begin Burst
External L H L L H
L
X
H
L L-H
Q
READ Cycle, Begin Burst
External L H L L H
L
X
H H L-H three-state
READ Cycle, Continue Burst Next
X X XL H
H
L
H
L L-H
Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05217 Rev. *C
Page 6 of 17
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