CY7C128A-25LMB データシートの表示（PDF） - Cypress Semiconductor

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CY7C128A-25LMB

2K x 8 Static RAM

Cypress Semiconductor 

CY7C128A

Switching Waveforms

Read Cycle No. 1[10,11]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2[10,12]

tRC

CE

DATA VALID

C128A–6

OE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

Write Cycle No. 1 (WE Controlled)[9,13]

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

50%

ICC

ISB

C128A–7

ADDRESS

CE

WE

DATA IN

DATA I/O

tWC

tSCE

tAW

tSA

DATA UNDEFINED

tHA

tPWE

tSD

tHD

DATAIN VALID

tHZWE

tLZWE

HIGH IMPEDANCE

Notes:

10. WE is HIGH for read cycle.

11. Device is continuously selected. OE, CE = VIL.

12. Address valid prior to or coincident with CE transition LOW.

13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.

C128A–8

4

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