CY7C1032-8 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1032-8 Datasheet PDF : 12 Pages
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Switching Waveforms (continued)
Output Timing (Controlled by CS)
CY7C1031
CY7C1032
CLK
ADSC
tADS
tADSH
CS
DATA OUT
tCSS
tCSH
tCDV
Output Timing (Controlled by WH/ WL)
CLK
ADSC and
ADSP
WH, WL
DATA OUT
tADS
tADSH
tWES
tWEH
tWEOZ
Truth Table
CS ADSP
H
X
H
L
Input
ADSC ADV
L
X
H
H
H
L
H
L
H
L
H
H
H
L
H
L
L
L
X
X
L
H
L
X
L
H
L
X
X
H
H
L
X
H
H
L
X
H
H
H
X
H
H
H
WH or WL
X
H
H
L
L
X
H
L
L
H
L
H
tADS tADSH
tCSS
tCSH
tCSOZ
tADS
tADSH
1031–12
tWEOV
1031–13
CLK
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
Address
N/A
Same address as
previous cycle
Incremented burst
address
Same address as
previous cycle
Incremented burst
address
External
External
External
Incremented burst
address
Incremented burst
address
Same address as
previous cycle
Same address as
previous cycle
Operation
Chip deselected
Read cycle (ADSP ignored)
Read cycle, in burst sequence
(ADSP ignored)
Write cycle (ADSP ignored)
Write cycle, in burst sequence
(ADSP ignored)
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Write cycle, in burst sequence
Read cycle, in burst sequence
Write cycle
Read cycle
11
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