CY7C026A(2000) データシートの表示（PDF） - Cypress Semiconductor
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CY7C026A Datasheet PDF : 17 Pages
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Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[24, 25, 26, 27]
tWC
ADDRESS
OE
[28,29]
CE
R/W
DATA OUT
DATA IN
tAW
tSA
tPWE[27]
NOTE 31
tHZWE[30]
tSD
CY7C026A
CY7C036A
tHZOE[30]
tHA
tLZWE
tHD
NOTE 31
Write Cycle No. 2: CE Controlled Timing[24, 25, 26, 32]
tWC
ADDRESS
[28,29]
CE
tSA
R/W
tAW
tSCE
tSD
DATA IN
tHA
tHD
Notes:
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tPWE.
28. To access RAM, CE = VIL, SEM = VIH.
29. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
30. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
31. During this period, the I/O pins are in the output state, and input signals must not be applied.
32. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
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