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CY7C026AV データシートの表示(PDF) - Cypress Semiconductor

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コンポーネント説明
一致するリスト
CY7C026AV
Cypress
Cypress Semiconductor Cypress
CY7C026AV Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
OUTPUT
C = 30 pF
3.3V
R1 = 590Ω
R2 = 435Ω
Figure 4. AC Test Loads and Waveforms
OUTPUT
RTH = 250Ω
C = 30pF
OUTPUT
VTH = 1.4V
C = 5 pF
3.3V
R1 = 590Ω
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
3 ns
3 ns
Switching Characteristics
Over the Operating Range [20]
Parameter
Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
-25
Unit
Min
Max
Min
Max
Read Cycle
tRC
tAA
tOHA
tACE[21]
tDOE
tLZOE[22, 23, 24]
tHZOE[22, 23, 24]
tLZCE[22, 23, 24]
tHZCE[22, 23, 24]
tPU[24]
tPD[24]
tABE[21]
Write Cycle
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
20
25
ns
20
25
ns
3
3
ns
20
25
ns
12
13
ns
3
3
ns
12
15
ns
3
3
ns
12
15
ns
0
0
ns
20
25
ns
20
25
ns
tWC
tSCE[21]
Write Cycle Time
CE LOW to Write End
20
25
ns
15
20
ns
tAW
Address Valid to Write End
15
20
ns
tHA
tSA[21]
Address Hold From Write End
Address Setup to Write Start
0
0
ns
0
0
ns
Notes
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
22. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
23. Test conditions used are Load 3.
24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
Document #: 38-06052 Rev. *J
Page 9 of 19
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