![](/html/Cypress/341342/page11.png)
Logic Block Diagrams (continued)
CY37256/CY37256V (256-lead BGA)
Clock/
Input Input
1
4
Ultra37000 CPLD Family
TDI
TCK
TMS
12 I/Os
I/O0−I/O11
12 I/Os
I/O12−I/O23
12 I/Os
I/O24−I/O35
12 I/Os
I/O36−I/O47
12 I/Os
I/O48−I/O59
12 I/Os
I/O60−I/O71
12 I/Os
I/O72−I/O83
12 I/Os
I/O84−I/O95
JTAG Tap
Controller
TDO
4
36
LOGIC
BLOCK 16
A
36
LOGIC
BLOCK 16
B
36
LOGIC
BLOCK
C
16
LOGIC
36
BLOCK 16
D
36
LOGIC
BLOCK 16
E
36
LOGIC
BLOCK 16
F
36
LOGIC
BLOCK 16
G
36
LOGIC
BLOCK 16
H
96
PIM
4
36
LOGIC
16 BLOCK
P
36
LOGIC
16 BLOCK
O
36
LOGIC
16 BLOCK
N
36
LOGIC
16 BLOCK
M
36
LOGIC
16 BLOCK
L
36
LOGIC
16 BLOCK
K
36
LOGIC
16 BLOCK
J
36
LOGIC
16 BLOCK
I
96
12 I/Os
I/O180−I/O191
12 I/Os
I/O168−I/O179
12 I/Os
I/O156−I/O167
12 I/Os
I/O144−I/O155
12 I/Os
I/O132−I/O143
12 I/Os
I/O120−I/O131
12 I/Os
I/O108−I/O119
12 I/Os
I/O96−I/O107
Document #: 38-03007 Rev. *D
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