CY22150FI データシートの表示（PDF） - Cypress Semiconductor

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CY22150FI

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

CY22150

Table 11.

CLKSRC2

0

0

0

0

1

1

1

1

CLKSRC1

0

0

1

1

0

0

1

1

CLKSRC0

Definition and Notes

0

Reference input.

1

DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are

4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.

0

DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.

1

DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.

0

DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are

4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.

1

DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.

0

DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.

1

Reserved – do not use.

Table 12.

Address

44H

45H

46H

D7

CLKSRC2

for LCLK1

CLKSRC0

for LCLK3

CLKSRC1

for CLK6

D6

CLKSRC1

for LCLK1

CLKSRC2

for LCLK4

CLKSRC0

for CLK6

D5

CLKSRC0

for LCLK1

CLKSRC1

for LCLK4

1

D4

CLKSRC2

for LCLK2

CLKSRC0

for LCLK4

1

D3

CLKSRC1

for LCLK2

CLKSRC2

for CLK5

1

D2

CLKSRC0

for LCLK2

CLKSRC1

for CLK5

1

D1

CLKSRC2

for LCLK3

CLKSRC0

for CLK5

1

D0

CLKSRC1

for LCLK3

CLKSRC2

for CLK6

1

Table 13. CLKOE Bit Setting

Address

D7

D6

09H

0

0

D5

CLK6

D4

CLK5

D3

LCLK4

D2

LCLK3

D1

LCLK2

D0

LCLK1

Programmable Interface Timing

The CY22150 utilizes a 2-wire serial-interface SDAT and

SCLK that operates up to 400 kbits/second in Read or Write

mode. The basic Write serial format is as follows.

Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); eight-bit Memory Address (MA); ACK;

eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;

eight-bit data in MA+2; ACK; etc. until STOP bit.The basic

serial format is illustrated in Figure 3.

Data Valid

Data is valid when the Clock is HIGH, and may only be transi-

tioned when the clock is LOW, as illustrated in Figure 2.

Data Frame

Every new data frame is indicated by a start and stop

sequence, as illustrated in Figure 4.

Data valid

Start Sequence – Start frame is indicated by SDAT going

LOW when SCLK is HIGH. Every time a Start signal is given,

the next eight-bit data must be the device address (seven bits)

and a R/W bit, followed by register address (eight bits) and

register data (eight bits).

Stop Sequence – Stop frame is indicated by SDAT going

HIGH when SCLK is HIGH. A Stop frame frees the bus for

writing to another part on the same bus or writing to another

random register address.

Acknowledge Pulse

During Write mode, the CY22150 will respond with an ACK

pulse after every eight bits. This is accomplished by pulling the

SDAT line LOW during the N*9th clock cycle, as illustrated in

Figure 5. (N = the number of eight-bit segments transmitted.)

During Read mode, the ACK pulse after the data packet is sent

is generated by the master.

Transition to next bit

SDAT

CLKHIGH

VIH

SCLK

VIL

tDH tSU

CLKLOW

Figure 2. Data Valid and Data Transition Periods

Document #: 38-07104 Rev. *F

Page 7 of 13

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