CXA2096 データシートの表示（PDF） - Sony Semiconductor

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CXA2096

Digital CCD Camera Head Amplifier

Sony Semiconductor 

CXA2096N

Description of Operation

Refer to the Block Diagram.

Operating Conditions

The camera signal processing system operates when PS is High.

Timing Chart (when VCC = 3V)

CCD output

Signal interval

Precharge level

OPB interval

Idle transfer

interval

Signal interval

SHP

SHD

SH1 output

SH2 output

SH3 output

CLPDM

(2µ dummy bit portion

during the idle transfer

interval)

AGC output

SH3 output

–SH2 output

× (–N)

XRS

CLPOB

(2µ during the OPB interval)

CAMSH output

PBLK

(10µ during the idle

transfer interval)

Signal level

2.1V

[∗1]

[∗2]

2.1V

Basic black

level

[∗3]

0.65V

2µs

Black level

2µs

0.65V

10µs

BLK SW output

1.35V

[∗4]

DRVOUT output

– 11 –

[∗5]

Approx. VRB + 35mV when OFFSET = 0V

Approx. VRB + 100mV when OFFSET = 1.5V

Applox. VRB when OFFSET = 3V

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