CS5101A データシートの表示（PDF） - Cirrus Logic
部品番号
コンポーネント説明
一致するリスト
CS5101A Datasheet PDF : 39 Pages
| |||
CS5101A CS5102A
ANALOG CHARACTERISTICS, CS5101A (Continued)
Parameter*
Symbol
Specified Temperature Range
-
Analog Input
Aperture Time
-
Aperture Jitter
-
Input Capacitance
(Note 5)
Unipolar Mode
-
Bipolar Mode
-
Conversion and Throughput
Conversion Time
Acquisition Time
Throughput
Power Supplies
(Note 6)
tc
(Note 7)
ta
(Note 8)
ftp
Power Supply Current
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
(Note 9)
Power Consumption
(Note 9, Note 10)
(SLEEP High)
(SLEEP Low)
Power Supply Rejection
(Note 11)
Positive Supplies
Negative Supplies
IA+
IA-
ID+
ID-
Pdo
Pds
PSR
PSR
CS5101A-J
Min Typ Max
0 to +70
- 25 -
- 100 -
- 320 425
- 200 265
-
- 8.12
-
- 1.88
100 -
-
- 21 28
- -21 -28
- 11 15
- -11 -15
- 320 430
-
1
-
- 84 -
- 84 -
CS5101A-B
Min Typ Max
-40 to +85
- 25 -
- 100 -
- 320 425
- 200 265
-
- 8.12
-
- 1.88
100 -
-
- 21 28
- -21 -28
- 11 15
- -11 -15
- 320 430
-
1
-
- 84 -
- 84 -
Unit
ºC
ns
ps
pF
pF
µs
µs
kSps
mA
mA
mA
mA
mW
mW
dB
dB
Notes: 5.
6.
7.
8.
9.
10.
11.
Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback
(FRN) mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge
of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5
master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the HOLD sample
rate is 100 kHz max.
The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN
mode allows 9 cycles for fine charge which provides for the minimum 1.125 µs with an 8MHz clock, however; in
PDT, RBT, or SSC modes and at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles.
This reflects the typical specification (6 clock cycles + 1.125 µs).
Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting
acquisition and conversion times, as described above.
All outputs unloaded. All inputs at VD+ or DGND.
Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB
in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency.
DS45F6
5
Share Link: 