CMX883 データシートの表示（PDF） - CML Microsystems Plc
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CMX883 Datasheet PDF : 58 Pages
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FRS Signalling Processor
1.3 Signal List (continued)
Package
D6, E1
Pin No.
10
Signal
Name
VBIAS
Type
O/P
11
DISC
I/P
12
DISC_FB
O/P
13
INPUT_2
I/P
14
INPUT_2_FB
O/P
15
MIC
I/P
16
MIC_FB
O/P
17
SIG_MONITOR
I/P
19
MOD_1
O/P
20
MOD_2
O/P
22
AUDIO
O/P
24
CLOCK/XTAL
I/P
25
CLOCK_OUT
O/P
26
I/P
27, 28
NC
CMX883
Description
Internally generated bias voltage of approximately VDD(A)/2,
except when bias is power-saved when VBIAS will discharge
to VSS(A). This pin should be decoupled to VSS(A) by a
capacitor mounted close to the device pins.
Input terminal of discriminator input amplifier.
Output / feedback terminal of discriminator input amplifier.
Input terminal of amplifier 2, for either a second microphone
or discriminator input.
Output / feedback terminal of input amplifier 2.
Input terminal of microphone input amplifier.
Output / feedback terminal of microphone input amplifier.
Signal Monitor input to the internal level detecting circuit.
Modulator 1 output.
Modulator 2 output.
Output of the audio section.
The input to the on-chip oscillator for an external crystal or a
clock circuit.
Buffered (un-inverted) clock output available for use by
other devices in the system.
Test input, connect to VSS(D).
No connection should be made to these pins.
Notes: I/P =
O/P =
T/S =
NC =
Input
Output
3-state Output
No Connection
2004 CML Microsystems Plc
9
D/883/7
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