CMX661 データシートの表示（PDF） - CML Microsystems Plc

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CMX661

PAIR GAIN DUAL SPM DETECTOR

CML Microsystems Plc 

Pair Gain Dual SPM Detector

CMX661

Package Package

D4

P3

Pin No. Pin No.

14

14

15

15

16

16

Signal

Description

Name

D1

SYSTEM

SELECT

VDD

Type

I/P

The MSB of the two bits which set the 'Will

Decode' bandwidth of the CMX661.

I/P

Selects the system frequency. High (logic ‘1’) =

12kHz; Low (logic ‘0’) = 16kHz. This signal has

an internal pullup resistor, so if left unconnected

the CMX661 will detect 12kHz by default.

POWER

The positive supply rail. Critical levels and

voltages within the CMX661 are dependent

upon this supply. This pin should be decoupled

to VSS by a capacitor mounted close to the

device pins.

Notes: I/P

O/P

BI

= Input

= Output

= Bidirectional

© 2002 CML Microsystems Plc

5

D/661/3

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