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CMX661(2001) データシートの表示(PDF) - CML Microsystems Plc

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CMX661
(Rev.:2001)
CML
CML Microsystems Plc CML
CMX661 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Pair Gain Dual SPM Detector
CMX661
1.7.1.3 Operating Characteristics (continued)
16kHz Detect Bandwidth
16kHz Detect Bandwidth
16kHz Not-Detect Frequencies (below 16kHz)
16kHz Not-Detect Frequencies (below 16kHz)
16kHz Not-Detect Frequencies (below 16kHz)
16kHz Not Detect Frequencies (below 16kHz)
16kHz Not-Detect Frequencies (above 16kHz)
16kHz Not-Detect Frequencies (above 16kHz)
16kHz Not-Detect Frequencies (above 16kHz)
16kHz Not-Detect Frequencies (above 16kHz)
Level Sensitivity
Level Sensitivity is set by external components
(see Figure 2)
Signal Quality Requirements for Correct
Operation (see Figure 2)
Signal to Noise Ratio (Amp input)
Signal to Voice Ratio (Amp input)
Signal to Voice Ratio (Amp output)
Notes
6, 11
6, 12
6, 9
6, 10
6, 11
6, 12
6, 9
6, 10
6, 11
6, 12
6, 7,
13
7, 14,
15, 16
7, 14,
15, 17
7, 14,
16, 17
Min.
15.20
14.80
16.64
16.88
17.20
17.60
-25
22.0
-36.0
-25.0
Typ.
-26.7
20.0
-40.0
-27.0
Max.
16.80
17.20
15.36
15.12
14.80
14.40
-28.5
Units
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
-29.0
dB
Notes:
1. At 5.0V. Not including any current drawn from the pins by external circuitry.
2. At 3.0V. Not including any current drawn from the pins by external circuitry.
3. Logic pins with no internal pullup or pulldown resistors: OP ENABLEN, D0 and D1.
4. Logic pins with an internal pullup or pulldown resistor: SYSTEM SELECT.
5. Time taken to change between high impedance and operating modes, with a maximum
capacitive load of 30pF on an output.
6. With adherence to Signal to Voice and Signal to Noise specifications.
7. 12kHz and/or 16kHz system.
8. The time delay after device powerup, change of bandwidth setting or change in input signal
conditions, before the condition of the outputs can be guaranteed correct.
9. With ‘Will Detect’ bandwidth set to ±1.5%.
10. With ‘Will Detect’ bandwidth set to ±3.0%.
11. With ‘Will Detect’ bandwidth set to ±5.0%.
12. With ‘Will Detect’ bandwidth set to ±7.5%.
13. With input amplifier gain setting of 0dB via external components and measured at amplifier
output with VDD =5.0V. Signal sensitivity is proportional to VDD.
14. For immunity to false responses and/or deresponses.
15. Common mode SPM and balanced voice signal.
16. With balanced SPM and voice signals. To avoid false deresponses due to saturation, the
peak to peak voice + noise level at the output of the input amplifier should be no greater than
the dynamic range of the device.
17. Maximum voice frequencies = 3.4kHz.
© 2001 Consumer Microcircuits Limited
14
D/661/2

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