Timing Diagram
VOUT
VPG
100%
90%
EN
PRELIMINARY
CM3112
PG
Inactive
Active
DPGD
DPGA
DPGD
Figure 1. Power Good Delay Timing
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com
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