CA3310AE データシートの表示（PDF） - Intersil
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CA3310AE Datasheet PDF : 15 Pages
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CA3310, CA3310A
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VDD. . . . . . . . . . . . . . . VSS -0.5V to VSS +7V
Analog Supply Voltage (VAA+) . . . . . . . . . . . . . . . . . . . . . VDD ±0.5V
Any Other Terminal . . . . . . . . . . . . . . . . .VSS -0.5V to VDD + 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Drain Current, per Output . . . . . . . . . . . . . . . . . . ±35mA
Total DC Supply or Ground Current . . . . . . . . . . . . . . . . . . . ±70mA
Operating Conditions
Temperature Range
Package Type D .
(TA)
....
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
-55oC
to
125oC
Package Type E, M . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
SBDIP Package . . . . . . . . . . . . . . . . . . . .
70
22
SOIC Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum
Maximum
Storage Temperature (TSTG)
Lead Temperature (Soldering
....
10s)
.
.
.
.
.
.
.
.
.
.
.-65oC
......
to
.
150oC
300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, VDD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
ACCURACY (See Text For Definitions)
Resolution
Differential Linearity Error CA3310
CA3310A
Integral Linearity Error
CA3310
CA3310A
Gain Error
CA3310
CA3310A
Offset Error
CA3310
CA3310A
ANALOG OUTPUT
Input Resistance
In Series with Input Sample
Capacitors
Input Capacitance
During Sample State
Input Capacitance
During Hold State
Input Current
Static Input Current
Input + Full-Scale Range
At VIN = VREF+ = 5V
At VIN = VREF - = 0V
STRT = V+, CLK = V+
At VIN = VREF+ = 5V
At VIN = VREF - = 0V
(Note 2)
Input - Full-Scale Range
(Note 2)
Input Bandwidth
From Input RC Time Constant
DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Over VDD = 3V to 6V (Note 2)
Low-Level Input Voltage
Over VDD = 3V to 6V (Note 2)
Input Leakage Current
Input Capacitance
Input Current
Except CLK
(Note 2)
CLK Only (Note 2)
MIN
TYP
MAX
UNITS
10
-
-
Bits
-
±0.5
±0.75
LSB
-
±0.25
±0.5
LSB
-
±0.5
±0.75
LSB
-
±0.25
±0.5
LSB
-
±0.25
±0.5
LSB
-
-
±0.25
LSB
-
±0.25
±0.5
LSB
-
-
±0.25
LSB
-
330
-
Ω
-
300
-
pF
-
20
-
pF
-
-
+300
µA
-
-
-100
µA
-
-
1
µA
-
-
-1
µA
VREF- +1
-
VDD +0.3
V
VSS -0.3
-
VREF+ -1
V
-
1.5
-
MHz
70
-
-
% of
VDD
-
-
30
% of
VDD
-
-
±1
µA
-
-
10
pF
-
-
±400
µA
6-9
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