VP306CG データシートの表示（PDF） - Mitel Networks
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VP306CG Datasheet PDF : 85 Pages
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DRAFT - PRELIMINARY DATA
VP305/6
NAME
ID
SCALE
SNR_THS
CR_OFFSET
CR_RP
CR_KP
CR_KD
CR_THSL
ADR
0
1
2
3
4
5
6
7
D7
D6
D5
D4
D3
D2
D1
D0 R/W
ID[7:0] Chip identification
R
SCALE[7:0] Scale factor for IOUT and QOUT outputs
R/W
SNR_THS[7:0] SNR estimator threshold
R/W
CR_OFFSET[7:0] Carrier loop DC offset compensation value
R/W
Reserved
CR_RP[3:0] Carrier reference period R/W
CR_KP[7:0] Carrier loop filter gain (P term)
R/W
CR_KD[7:0] Carrier loop filter gain (D term)
R/W
CR_THSL[7:0] Carrier lock detector threshold
R/W
Table 5d Register bank 2. BANK[5:3] = 16.
NAME
ID
CR_SWR
CR_USWL U
CR_USWL L
CR_LSWL U
CR_LSWL L
CR_CONFIG
CONFIG
ADR
0
1
2
3
4
5
6
7
D7
D6
D5
D4
D3
D2
D1
D0
ID[7:0] Chip identification
CR_SWR[7:0] Carrier sweep rate
Reserved
CR_USWL[13:8] Carrier Upper sweep limit (upper nibble)
CR_USWL[7:0] Carrier Upper sweep limit (lower byte)
Reserved
CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble)
CR_LSWL[7:0] Carrier Lower sweep limit (lower byte)
CR_CONFIG[7:0] Carrier configuration
CONFIG[7:0] Configuration
Table 5e. Register bank 3. BANK[5:3] = 24.
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NAME
ADR
ID
0
VIT_ERR_C H 1
VIT_ERR_C L 2
RS_UBC
3
Not used 4 - 7
D7
D6
D5
D4
D3
D2
D1
D0 R/W
ID[7:0] Chip identification
R
VERRC[15:8] - Viterbi error count high byte
R
VERRC[7:0] - Viterbi error count low byte
R
RSUBC[7:0] - Reed Solomon uncorrected block count
R
Writing to these addresses will have no effect. Reading will return 255
R/W
Table 5f. Register bank 4. BANK[5:3] = 32.
Note: In Bank 4, the registers 1 to 3 are READ only and registers 4 to 7 are not used. Writing to
these addresses will have no effect.
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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