VP306S データシートの表示（PDF） - Mitel Networks

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VP306S

Satellite Channel Decoder

Mitel Networks 

VP305/6

DRAFT - PRELIMINARY DATA

2. REGISTER DETAILS

2.1. Parallel interface register map.

The default state of almost all of the registers is zero, except the ID register and unused registers.

Reserved or unused bits should be set to zero when writing to a register.

NAME

ADR D7

D6

D5

D4

D3

D2

D1

D0 R/W

BANK

0

Reserved

AD5

AD4

AD3

Reserved

W

Table 5a. BANK Register 0. (Address byte = 0, Data byte = NEXT BANK)

NAME

ADR D7

D6

D5

D4

D3

D2

D1

D0 R/W

ID

0

ID[7:0] Chip identification

R

INT_QPSK 1

INT_QPSK[7:0] Interrupt QPSK

R

INT_FEC

2

INT_FEC[7:0] Interrupt FEC

R

STATUS

3 Reserved

STATUS[6:0]

R

AGC_LVL

4

AGC_LVL[7:0] AGC loop voltage meter

R

CR_VCOF U 5

Reserved

CR_VCOF[13:8] Measured VCO frequency (upper nibble) R

CR_VCOF L 6

CR_VCOF[7:0] Measured VCO frequency (lower byte)

R

IE_QPSK

7

IE_QPSK[7:0] Interrupt enable QPSK

R/W

Table 5b. Register bank 0. BANK[5:3] = 0.

Note: In Bank 0, the registers 1 to 6 are READ only. Writing to these addresses will have no

effect.

NAME

ADR

ID

0

SYM_CONFIG 1

SYM_RP

2

SYM_NF U 3

SYM_NF L 4

SYM_RATIO 5

AGC_REF 6

AGC_BW

7

D7

D6

D5

D4

D3

D2

D1

D0 R/W

ID[7:0] Chip identification

R

Reserved

SYM_CONFIG[5:0] Symbol configuration

R/W

Reserved

SYM_RP[3:0] Symbol AFC reference R/W

period

SYM_NF[15:8] Symbol input nominal frequency (upper byte)

R/W

SYM_NF[7:0] Symbol input nominal frequency (lower byte)

R/W

Reserved

SYM_RATIO[2:0]

R/W

AGC_REF[7:0] Reference AGC level

R/W

Reserved

INT_DC

AGC_BW[2:0]

R/W

Table 5c. Register bank 1. BANK[5:3] = 8.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

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