BS616LV1611 データシートの表示（PDF） - Brilliance Semiconductor

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BS616LV1611

Very Low Power CMOS SRAM 1M X 16 bit

Brilliance Semiconductor 

WRITE CYCLE 2 (1,6)

ADDRESS

CE1

CE2

LB, UB

WE

DOUT

DIN

tWC

tCW(11)

(5)

BS616LV1611

tCW(11)

tBW

(12)

tAW

tWP(2)

tAS

tWHZ(4,10)

tWR(3)

tOW

(7)

(8)

tDW

tDH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and

WE low. All signals must be active to initiate a write and any one signal can terminate a

write by going inactive. The data input setup and hold timing should be referenced to the

second transition edge of the signal that terminates the write.

3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of

write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL).

7. DOUT is the same phase of write data of this write cycle.

8. DOUT is the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the

data input signals of opposite phase to the outputs must not be applied to them.

10.Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

12.The change of Read/Write cycle must accompany with CE or address toggled.

R0201-BS616LV1611

8

Revision 2.3

May.

2006

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