BD9202EFS データシートの表示（PDF） - ROHM Semiconductor
部品番号
コンポーネント説明
一致するリスト
BD9202EFS Datasheet PDF : 20 Pages
| |||
BD9202EFS
Technical Note
●Usage Notes
1.) Absolute Maximum Ratings
Although the quality of this product has been tightly controlled, deterioration or even destruction may occur if the absolute maximum ratings,
such as for applied pressure and operational temperature range, are exceeded. Furthermore, we are unable to assume short or open
mode destruction conditions. If special modes, which exceed the absolute maximum ratings, are expected, physical safely precautions
such as fuses should be considered.
2.) Reverse Connection of Power Supply Connector
The IC can destruct from reverse connection of the power supply connector. Precautions, such as inserting a diode between the external
power supply and IC power terminal, should be taken as protection against reverse connection destruction.
3.) Power Supply Line
Because there is a return of current regenerated by back EMF of the external coil, the capacity value should be determined after confirming
that there are no problems with characteristics such as capacity loss at low temperatures with electrolysis condensers, for example by
placing a condenser between the power supply and GND as a route for the regenerated current.
4.) GND Potential
The potential of the GND pin should be at the minimum potential during all operation status
5.) Heat Design
Heat design should consider power dissipation (Pd) during actual use and margins should be set with plenty of room.
6.) Short-circuiting Between Terminals and Incorrect Mounting
When attaching to the printed substrate, pay special attention to the direction and proper placement of the IC. If the IC is attached
incorrectly, it may be destroyed.
Destruction can also occur when there is a short, which can be caused by foreign objects entering between outputs or an output and the
power GND.
7.) Operation in Strong Magnetic Fields
Exercise caution when operating in strong magnet fields, as errors can occur.
8.) ASO
When using this IC, it should be configured so that the output Tr should not exceed absolute maximum ratings and ASO. With CMOS ICs
and ICs that have multiple power sources, there is a chance of rush current flowing momentarily, so exercise caution with power supply
coupling capacity, power supply and width of GND pattern wiring and its layout.
9.) Heat Interruption Circuit
This IC has a built-in Temperature Protection Circuit (TSD circuit). The temperature protection circuit (TSD circuit) is only to cut off the IC
from thermal runaway, and has not been designed to protect or guarantee the IC. Therefore, the user should not plan to activate this
circuit with continued operation in mind.
10.) Inspection of Set Substrates
If a condenser is connected to a pin with low impedance when inspecting the set substrate, stress may be placed on the IC, so there
should be a discharge after each process. Furthermore, when connecting a jig for the inspection process, the power must first be turned
OFF before connection and inspection, and turned OFF again before removal.
11.) IC Terminal Input
This IC is a monolithic IC, and between each element there is a P+ isolation and P substrate for element separation.
There is a P-N junction formed between this P-layer and each element’s N-layer, which makes up various parasitic elements.
For example, when resistance and transistor are connected with a terminal as in figure 15:
〇When GND>(terminal A) at the resistance, or GND>(terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode.
〇Also, when GND>(terminal B) at the transistor, a parasitic NPN transistor operates by the N-layer of other elements close to the
aforementioned parasitic diode.
With the IC’s configuration, the production of parasitic elements by the relationships of the electrical potentials is inevitable. The operation
of the parasitic elements can also interfere with the circuit operation, leading to malfunction and even destruction. Therefore, uses that
cause the parasitic elements to operate, such as applying voltage to the input terminal that is lower than the GND (P-substrate), should be
avoided.
(Terminal A)
Resistance
Transistor (NPN)
B
(Terminal B) C
E
P＋
N
P
N
P＋
N
P＋
Ｎ
N
P
N
GND
P＋
N
(Terminal A)
Parasitic Element
P board
Parasitic Element
P board
GND
GND
Parasitic Element
Fig.32 Simple Structure of Bipolar IC
12.) Earth Wiring Pattern
Where there are both a small signal GND and a large current GND, it is recommended that large current GND pattern and
small signal GND pattern are separated, and that there is an earth at the set’s control point so that the pattern wiring’s
resistance and voltage change from the large current doesn’t change the small signal GND’s voltage. Ensure that the
GND wiring patterns for external parts do not fluctuate.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
18/19
2009.04 - Rev.A
Share Link: 