PDI1394P11 データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
一致するリスト
PDI1394P11 Datasheet PDF : 20 Pages
| |||
Philips Semiconductors
3-port physical layer interface
Product specification
PDI1394P11
20.0 STATUS REQUEST, LENGTH OF STREAM: 16 BITS
BIT(S) NAME
DESCRIPTION
0
Arbitration reset gap Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is
defined in the P1394 standard). This bit is used by the link in its busy/retry state machine.
1
Subaction gap
Indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined
in the P1394 standard). This bit is used by the link to detect the completion of an isochronous cycle.
2
Bus Reset
Indicates that the phy has entered the bus reset state.
3
State Time out or
Indicates that the phy stayed in a particular state for too long a period, which is usually the effect of a loop
CPS
in the cable topology, or that the cable power has dropped below the threshold for reliable operation.
4–7
Address
These bits hold the address of the phy register whose contents will be transferred to the link.
8–15 Data
The data that is to be sent to the link.
21.0 STATUS TRANSFER TIMING
PHY
CTL [0:1]
00
01
01
01
00
00
PHY
D [0:1]
00
S[0,1]
S[2,3]
S[14,15]
00
Figure 7. Status Transfer Timing
00
SV00233
1999 Apr 09
15
Share Link: 