MXD1013UA070 データシートの表示（PDF） - Maxim Integrated
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MXD1013UA070 Datasheet PDF : 6 Pages
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3-in-1 Silicon Delay Line
tRISE
VIH
IN
VIL
OUT
PERIOD
tFALL
2.4V 2.4V
1.5V
1.5V
1.5V
0.6V
0.6V
tWI
tPHL
tPLH
1.5V 1.5V
Figure 1. Timing Diagram
PULSE
GENERATOR
50Ω
PULSE
GENERATOR
50Ω
PULSE
GENERATOR
50Ω
TIME
INTERVAL
COUNTER
MXD1013
TD
TD
TD
74F04
74F04
74F04
EACH OUTPUT IS LOADED WITH THE EQUIVALENT OF ONE 74F04.
THE DELAY OF THE 74F04 IS SUBTRACTED FROM THE MEASURED DELAY.
Figure 2. Test Circuit
__________ Applications Information
Supply and Temperature
Effects on Delay
Over the specified range, the MXD1013’s delays are
typically 2% accurate. Variations in supply voltage may
affect the MXD1013’s fixed output delays. Supply volt-
ages beyond the specified range may result with larger
variations. Although there might be a slight variance in
delays over temperature, the MXD1013 is internally
compensated to maintain its nominal values.
Loading Effect on Delay Lines
Capacitive loads increase delay times as they increase
the rise and fall times of the delay lines. Other logic
devices increase the capacitance at the output of the
delays, which can affect device performance.
Board Layout Considerations
Bypass the MXD1013 with a 0.1µF capacitor to mini-
mize the impact of high-speed switching on the power
supply. The power supply must be able to deliver the
required switching currents for proper operation.
It is advisable to minimize trace lengths in order to
reduce board capacitance as well as the traveling dis-
tance between devices. Sockets and wire-wrapped
boards increase capacitance and should be avoided.
___________________Chip Information
TRANSISTOR COUNT: 824
_______________________________________________________________________________________ 5
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