MC100E337FN(2006) データシートの表示（PDF） - ON Semiconductor

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MC100E337FN
(Rev.:2006)

5VECL 3-Bit Scannable Registered Bus Transceiver

ON Semiconductor 

MC100E337

PIN DESCRIPTION

PIN

A0 − A2

B0 − B2

S-IN

TEN, REN

SCAN

ABUSDIS

SBUSEN

SYNCEN

CLK

BUS0 − BUS2

Q0 − Q2

FUNCTION

ECL Data Inputs A

ECL Data Inputs B

ECL Serial (Scan) Data Input

HOLD/LOAD Controls

ECL Scan Control

ECL Asynchronous Bus Disable

ECL Synchronous Bus Enable

ECL Synchronous Enable Control

ECL Clock

ECL 25Ω Cutoff Bus Outputs

ECL Receive Data Outputs

(Q2 serves as SCAN_OUT in scan mode)

VCC, VCCO

VEE

GND

Positive Supply

Negative Supply

Ground

B0 A0

VCCO Q0

25 24 23 22 21 20 19

SCAN 26

18 GND

S-IN 27

17 BUS0

TEN 28

VEE 1

REN 2

CLK 3

Pinout: 28-Lead PLCC

(Top View)

16 VCC

15 Q1

14 VCCO

13 BUS1

A1 4

12 GND

5 6 7 8 9 10 11

B1 A2 B2 VCCO BUS2 GND Q2

* All VCC and VCCO pins are tied together on the die.

Warning: All VCC, VCCO, and VEE pins must be externally

connected to Power Supply to guarantee proper operation.

Figure 1. Pinout Assignment

AB22

DQ

BUS2

DQ

Q2/

SCAN_OUT

AB11

DQ

BUS1

DQ

Q1

AB00

S_IN

TEN

REN

SCAN

ABUSDIS

SBUSEN

SYNCEN

CLK

BUS0

DQ

DQ

Q0

DQ

SET

Figure 2. Logic Diagram

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