MC10E336FN データシートの表示（PDF） - ON Semiconductor
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MC10E336FN Datasheet PDF : 8 Pages
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MC10E336, MC100E336
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
TEN2 TEN1 B2
25 24 23
BUSEN1 26
A2 NC VCCO Q2
22 21 20 19
18
GND
BUSEN2 27
17 BUS2
RXEN 28
16 VCC
VEE 1
CLK1 2
Pinout: 28-Lead PLCC
(Top View)
15 Q1
14 VCCO
CLK2 3
13 BUS1
A0 4
12 GND
5 6 7 8 9 10 11
B0 A1 B1 VCCO BUS0 GND Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
TEN1, TEN2
A0–A2
B0–B2
Q0–Q1
BUSEN1, BUSEN2
BUS0–BUS2
RXEN
CLK1, CLK2
VCC, VCCO
VEE
GND
NC
FUNCTION
ECL Transit Enable
ECL Data Inputs A
ECL Data Inputs B
ECL Output
ECL Bus Enables
ECL Bus Outputs
ECL Receive Enable
ECL Clock Input
Positive Supply
Negative Supply
Ground
No Connect
AB00
AB11
AB22
TEN1
TEN2
RXEN
BUSEN1
BUSEN2
CLK1
CLK2
LOGIC DIAGRAM
0 DQ
1
0 DQ
1
0
DQ
1
25 W CUTOFF BUS0
D
Q
50 W Q0
25 W CUTOFF
BUS1
D
50 W
Q
Q1
25 W CUTOFF
BUS2
D
50 W
Q
Q2
DQ
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