AT5FC512-20 データシートの表示（PDF） - Atmel Corporation
部品番号
コンポーネント説明
一致するリスト
AT5FC512-20 Datasheet PDF : 15 Pages
| |||
Memory Card Operations (Continued)
Read Enable/Output Disable
Data outputs from the card are disabled when OE is at a
logic-high level. Under this condition, outputs are in the
high-impedance state. The A18 selects the paired mem-
ory chip segments, while A0 decides the upper or lower
bank. The CE1/CE2 pins determine either byte or word
mode operation. The Output Enable (OE) is forced low to
activate all outputs of the memory chip segments. The on-
card I/O transceiver is set in the output mode. The
AT5FC512 sends data to the host. Refer to AC Read
Waveforms drawing.
Standby Operations
When both CE1 a n d CE2 are at logic-high level, the
AT5FC512 is in Standby mode; i.e., all memory chip seg-
ments as well as the decoder/transceiver are completely
de-selected at minimum power consumption. Even in the
byte-mode read operation, only one memory chip seg-
ment (even or odd) is active at any time. The other seven
memory chip segments remain in standby. In the word-
mode there are two memory chip segments in active and
six in standby.
Write Operations
The AT5FC512 is written on a sector basis. Each sector of
256 bytes can be selected randomly and written inde-
pendently without any prior erase cycle. A8 to A17 specify
the sector address, while A18 specifies the Flash chip
segment pair. Within each sector, the individual byte ad-
dress is latched on the falling edge of CE or WE, which-
ever occurs last. The data is latched by the first rising edge
of CE or WE. Each byte pair to be programmed must have
its high-to-low transition on WE (or CE) within 150 µs of
the low-to- high transition of WE (or CE) of the preceding
byte pair. If a high-to-low transition is not detected within
150 µs of the last low-to-high transition, the data load pe-
riod will end and the internal programming period will start.
All the bytes of a sector are simultaneously programmed
during the internal programming period. A maximum write
time of 10 ms per sector is self-controlled by the Flash
devices. Refer to AC Write Waveforms drawings.
Write Protection
The AT5FC512 has five types of write protection. The
PCMCIA/JEIDA socket itself provides the first type of write
protection. Power supply and control pins have specific
pin lengths in order to protect the card with proper power
supply sequencing in the case of hot insertion and re-
moval.
A mechanical write protection switch provides a second
type of write protection. When this switch is activated, WE
is internally forced high. The Flash memory arrays are
therefore write-disabled.
The third type of write protection is achieved with the built-
in low VCC sensing circuit within each Flash device. If the
external VCC is below 3.8V (typical), the write function is
inhibited.
The fourth type of write protection is a noise filter circuit
within each Flash device. Any pulse of less than 15 ns
(typical) on the WE, CE1 or CE2 inputs will not initiate a
program cycle.
The last type of write protection is based on the Software
Data Protection (SDP) scheme of the AT29C010A de-
vices. Each of the sixteen devices needs to enable and
disable the SDP individually. Refer to the Software Data
Protected Programming/Disable Algorithm tables for
descriptions of enable and disable SDP operations.
Card Detection
Each CD (output) pin should be read by the host system
to determine if the memory card is properly seated in the
socket. CD1 and CD2 are internally tied to the ground. If
both bits are not detected, the system should indicate that
the card must be re-inserted.
CIS Data
The Card Information Structure (CIS) describes the capa-
bilities and specifications of a card. The CIS of the
AT5FC512 can be written either by the OEM or by Atmel
at the attribute memory space beginning at address
00000H by using a format utility. The AT5FC512 contains
a separate 2K byte EEPROM memory for the card’s attrib-
ute memory space. The attribute is active when the REG
pin is driven low. D0-D7 are active during attribute mem-
ory access. D8-D15 should be ignored. Odd order bytes
present invalid data. Refer to the Attribute Memory
Operations table.
6
AT5FC512
Share Link: 