AS1160-BCTT データシートの表示（PDF） - austriamicrosystems AG

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AS1160-BCTT

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Pinout

Figure 3. AS1161 Pin Assignments (Top View)

A1

A2

A3

A4

A5

A6

A7

DGND N/C REFCLK AGND ROUT1 DGND DVDD

B1

B2

B3

B4

B5

B6

B7

AVDD AGND RCKR/FN ROUT2 DGND ROUT3 DVDD

C1 C2 C3 C4 C5 C6 C7

RI- AVDD N/C ROUT0 DVDD DVDD ROUT4

D1

REN

D2 D3 D4 D5 D6 D7

RI+ PWDNN N/C DVDD ROUT5 DGND

E1

E2

E3

E4

E5

E6

E7

LOCKN RCLK N/C DGND TCK TRSTN DGND

F1

F2

F3

F4

F5

F6

F7

AVDD AVDD AGND AGND ROUT8 TDI ROUT6

G1 G2 G3 G4 G5 G6 G7

AVDD AGND DGND ROUT9 ROUT7 TDO TMS

Table 2. AS1161 Pin Descriptions

Pin Number Pin Name

Description

ROUT0:ROUT9 Data Output. ±4mA CMOS level outputs.

Recovered Clock Rising/Falling Strobe Select. LVTTL level input. Selects RCLK

RCKR/FN

active edge for strobing of ROUT0:ROUT9 data.

1 = Rising edge.

0 = Falling edge.

REFCLK Reference Clock Input. LVTTL level input. Input for 20MHz - 66MHz system clock.

RI+

+ Serial Data Input. Non-inverting Bus LVDS differential input.

RI-

- Serial Data Input. Inverting Bus LVDS differential input.

PWDNN

Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states

the outputs and puts the device into low power sleep mode.

LOCKN

Lock. CMOS level output. This signal goes low when the deserializer PLL locks onto

the embedded clock edge.

RCLK

Recovered Clock. CMOS level output. Parallel data rate clock recovered from

embedded clock. Used to strobe ROUT0:ROUT9.

See Figure 3

REN

Output Enable. LVTTL level input. If REN is set to logic low ROUT0:ROUT9 and RCLK

are in tri-state condition.

DVDD

+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital

circuitry.

DGND

Digital Circuit Ground

+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD

AVDD

should be at the same potential and must not be more than 0.3V apart even on

transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.

AGND

Analog Ground (PLL and Analog Circuits).

TDI

IEEE 1149.1 Test Data Input

TDO

IEEE 1149.1 Test Data Output

TMS

IEEE 1149.1 Test Mode Select Input

TCK

IEEE 1149.1 Test Clock Input

TRSTN IEEE 1149.1 Test Reset Input

N/C

No Connection. Leave open-circuit, do not connect these pins.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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