AS1115-BQFT(2012) データシートの表示（PDF） - austriamicrosystems AG

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AS1115-BQFT
(Rev.:2012)

64 LEDs, I²C Interfaced LED Driver with Keyscan

austriamicrosystems AG 

AS1115

Datasheet - Detailed Description

I²C Interface

The AS1115 supports the I²C serial bus and data transmission protocol in high-speed mode at 3.4MHz. The AS1115 operates as a slave on the

I²C bus. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START

and STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.

Figure 18. I²C Interface Initialization

1

89 1

89

lid 0 0 0 0 0 A1 A0 R/W

a Default values at power up: A1 = A0 = 0

D15 D14 D13 D12 D11 D10 D9 D8

v Figure 19. Bus Protocol

till SDI

MSB

Slave Address

G s R/W

A t Direction Bit

ACK from

Receiver

ACK from

Receiver

s n SCL

am nte START

1

2

6

7

8

9

ACK

1

2 3-8 8

9

ACK

Repeat if More Bytes Transferred

STOP or

Repeated

START

The bus protocol (as shown in Figure 19) is defined as:

o - Data transfer may be initiated only when the bus is not busy.

c - During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is

HIGH will be interpreted as control signals.

l The bus conditions are defined as:

- Bus Not Busy. Data and clock lines remain HIGH.

a - Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

ic - Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the

HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred

n between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and

each receiver acknowledges with a ninth-bit.

h Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.

- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The mas-

c ter device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge

Teclock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generat-

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