APL5315-12BITRL データシートの表示（PDF） - Anpec Electronics
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APL5315-12BITRL Datasheet PDF : 16 Pages
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APL5315
Application Information
Input Capacitor
The APL5315 requires proper input capacitors to supply
surge current during stepping load transients to prevent
the input rail from dropping . Because the parasitic induc-
tor from the voltage sources or other bulk capacitors to
the VIN limit the slew rate of the surge current. Place the
Input capacitors near VIN as close as possible. Input
capacitors should be larger than 1µF and a minimum
ceramic capacitor of 1µF is necessary.
Output Capacitor
The APL5315 needs a proper output capacitor to main-
tain circuit stability and to improve transient response over
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is suffi-
cient at all operating temperatures. Large output capaci-
tor value can reduce noise and improve load-transient
response and PSRR, however it also affects power on
issue. Equation (1) shows the relationship between the
maximum COUT value and VOUT.
COUT(max)
=
87 ⋅ 0.55 -
0.1155
VOUT
..................(1)
Where
the
unit
of
C is
OUT
µF
and
V is
OUT
V
.
Figure
1
shows
the curve of maximum output capacitor over the output
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should be under the line. Out-
put capacitors must be placed at the load and ground pin
as close as possible and the impedance of the layout
must be minimized.
48
45
42
39
36
33
30
0
1
2
3
4
5
6
Output voltage (V)
Figure 1
Operation Region and Power dissipation
The APL5315 maximum power dissipation depends
on the thermal resistance and temperature difference
between the die junction and ambient air. The power dis-
sipation PD across the device is:
PD
=
(TJ
-
TA)
/
θ
JA
where (TJ-TA) is the temperature difference between the
junction
and
ambient
air.
θ
JA
is
the
thermal
resistance
between Junction and ambient air. Assuming the
TA=25oC and maximum TJ=160oC (typical thermal limit
threshold), the maximum power dissipation is calcu-
lated as:
P =(160-25)/240
D(max)
= 0.56(W)
For normal operation, do not exceed the maximum junc-
tion temperature rating of TJ = 125 oC. The calculated power
dissipation should less than:
PD =(125-25)/240
= 0.41(W)
The GND provides an electrical connection to ground and
channels heat away. Connect the GND to ground by
using a large pad or ground plane.
Layout Considerations
Figure 2 illustrates the layout. Below is a checklist for
yours layout:
1. Please place the input capacitors close to the VIN.
2. Ceramic capacitors for load must be placed near
the load as close as possible.
3. To place APL5315 and output capacitors near the
load is good for performance.
4. Large current paths, the bold lines in figure 2,
must have wide tracks.
5. Divider resistor R1 and R2 must be placed near
the SET as close as possible.
Copyright © ANPEC Electronics Corp.
10
Rev. A.2 - Mar., 2007
www.anpec.com.tw
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