AMMC0XXA データシートの表示（PDF） - Advanced Micro Devices
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AMMC0XXA Datasheet PDF : 39 Pages
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PRELIMINARY
Data Protection
An optional mechanical write protect switch provides
user-initiated write protection. When this switch is acti-
vated, WE# is internally forced high. The Flash memory
command register is disabled from accepting any write
commands. This prevents the card from responding to
any commands (for example, an Autoselect command).
See Figure 3.
Write Enabled
Write Disabled
20975D-4
Figure 3. Write Protect Switch
(Card Right Side View)
In addition to card-level data protection, AMD Flash
Miniature Cards offer several device-level data protec-
tion features.
Device-Level Data Protection
AMD Flash memory devices offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. During power up, each device automatically
resets the internal state machine to the read mode. The
control register architecture allows alteration of the
memory contents only occurs after successful comple-
tion of specific multi-bus cycle command sequences.
AMD Flash memory devices also incorporate the fol-
lowing features to prevent inadvertent write cycles
resulting from VCC power-up and power-down
transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-
up and power-down, the AMD memory devices in
the Miniature Card lock out write cycles for VCC <
VLKO (see “DC Characteristics” on page 25 for volt-
ages). When VCC < VLKO, the command register is
disabled, all internal program/erase circuits are dis-
abled, and the device resets to the read mode.
These memory devices ignore all writes until VCC >
VLKO. The user must ensure that the control pins
are in the correct logical state when VCC > VLKO to
prevent unintentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# will neither initiate a write cycle nor change the
command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH, or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
Power-Up Write Inhibit
Power-up of the device with CE# = WE# = VIL and OE#
= VIH will not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
Read Mode
Two Card Enable (CE#) pins are available on the
memory card. Both CE# pins must be active low for
word-wide read accesses. Only one CE# is required for
byte-wide accesses. The CE# pins select and deter-
mine when to apply power to the high-byte and low-
byte memory devices. The Output Enable (OE#) con-
trols gating accessed data from the memory device
outputs.
The Miniature card automatically powers up in the
read/reset state. In this case, a command sequence is
not required to read data. Standard microprocessor
read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the
AC Read Characteristics and Waveforms for the spe-
cific timing parameters.
Output Disable
Data outputs from the card are disabled when OE# is
at a logic-high level. Under this condition, outputs are in
the high-impedance state.
Standby Operations
Byte-wide read accesses only require half of the
read/write output buffer (x16) to be active. In addition,
only one memory device is active within either the high
order or low order bank. Activation of the appropriate
half of the output buffer is controlled by the combination
of both CE# pins. The CE# pins also control power to
the high and low-order banks of memory. Outputs of
the memory bank not selected are placed in the high
impedance state. The individual memory device is acti-
vated by the address decoders. The other memory
devices operate in standby. An active memory device
continues to draw power until completion of a write or
erase operation if the card is de-selected in the process
of one of these operations.
AmMC0XXA
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