AM79C970 データシートの表示（PDF） - Advanced Micro Devices

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AM79C970

PCnet™-PCI Single-Chip Ethernet Controller for PCI Local Bus

Advanced Micro Devices 

AMD

Figure D3 shows the event flow for the two-interrupt method:

Ethernet

Wire

activity:

Ethernet

Controller

activity:

Software

activity:

S10: Driver sets up TX descriptor.

} C10: ERP interrupt

is generated.

C9: Controller writes descriptor #3.

N2: EOM

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

C7: Controller writes descriptor #2.

Buffer

#3

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2.

C4: Lookahead to descriptor #3 (OWN).

} C3: SRP interrupt

is generated.

C2: Controller writes descriptor #1.

Buffer

#2

S9: Application processes packet, generates TX packet.

{ S8: Driver calls application

to tell application that

S8A: Interrupt latency. packet has arrived.

S7: Driver is swapped out, allowing a non-Etherenet

application to run.

{ S7A: Driver Interrupt Service

Routine executes

RETURN.

S6: Driver copies data from buffer #2 to the application buffer.

S5: Driver polls descriptor #2.

S4: Driver copies data from buffer #1 to the application buffer.

} { S3: Driver writes modified application

pointer to descriptor #3.

S2: Driver call to application to

get application buffer pointer.

S1: Interrupt latency.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

Buffer

#1

S0: Driver is idle.

C0: Lookahead to descriptor #2.

{N1: 64th byte of packet

data arrives.

N0: Packet preamble, SFD

and destination address

are arriving.

Figure D3. LAPP Timeline for TWO-INTERRUPT Method

18220A-57

1-1030

Am79C970

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