AT5FC001-20 データシートの表示（PDF） - Atmel Corporation
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AT5FC001-20 Datasheet PDF : 14 Pages
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Memory Card Operations
The AT5FC001 Flash Memory Card is organized as an array of
eight individual AT29C010A devices. They are logically de-
fined as contiguous sectors of 256 bytes. Each sector can be read
and written randomly as designated by the host. There is NO
need to erase any sector prior to any write operation. Also, there
is NO high voltage (12 V) required to perform any write opera-
tions.
The common memory space data contents are altered in a simi-
lar manner as writing to individual Flash memory devices. On-
card address and data buffers activate the appropriate Flash de-
vice in the memory array. Each device internally latches address
and data during write cycles. Refer to the Memory Operations
Table.
Byte-Wide Operations
The AT5FC001 provides the flexibility to operate on data in
byte-wide or word-wide operations. Byte-wide data is available
on D0-D7 for read and write operations (CE1 = low, CE2 =
high). Even and odd bytes are stored in a pair of memory chip
segments (i.e., S0 and S1) and are accessed when A0 is low and
high respectively.
Word-Wide Operations
The 16-bit words are accessed when both CE1 and CE2 are
forced low, A0 = don’t care. D0-D15 are used for word-wide
operations
Read Enable/Output Disable
Data outputs from the card are disabled when OE is at a logic-
high level. Under this condition, outputs are in the high-imped-
ance state. The A18 and A19 select the paired memory chip seg-
ments, while A0 decides the upper or lower bank. The CE1/CE2
pins determine either byte or word mode operation. The Output
Enable (OE) is forced low to activate all outputs of the memory
chip segments. The on-card I/O transceiver is set in the output
mode. The AT5FC001 sends data to the host. Refer to A.C.
Read Waveforms drawing.
Standby Operations
When both CE1 and CE2 are at logic-high level, the AT5FC001
is in Standby mode; i.e., all memory chip segments as well as the
decoder/transceiver are completely de-selected at minimum
power consumption. Even in the byte-mode read operation, only
one memory chip segment (even or odd) is active at any time.
The other seven memory chip segments remain in standby. In
the word-mode there are two memory chip segments in active
and six in standby.
Write Operations
The AT5FC010 is written on a sector basis. Each sector of 256
bytes can be selected randomly and written independently with-
out any prior erase cycle. A8 to A17 specify the sector address,
while A18 and A19 specify the Flash chip segment pair. Within
each sector, the individual byte address is latched on the falling
edge of CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. Each byte pair to be pro-
grammed must have its high-to-low transition on WE (or CE)
within 150 µs of the low-to- high transition of WE (or CE) of the
preceding byte pair. If a high-to-low transition is not detected
within 150 µs of the last low-to-high transition, the data load
period will end and the internal programming period will start.
All the bytes of a sector are simultaneously programmed during
the internal programming period. A maximum write time of 10
ms per sector is self-controlled by the Flash devices. Refer to
A.C. Write Waveforms drawings.
Write Protection
The AT5FC001 has five types of write protection. The
PCMCIA/JEIDA socket itself provides the first type of write
protection. Power supply and control pins have specific pin
lengths in order to protect the card with proper power supply
sequencing in the case of hot insertion and removal.
A mechanical write protection switch provides a second type of
write protection. When this switch is activated, WE is internally
forced high. The Flash memory arrays are therefore write-dis-
abled.
The third type of write protection is achieved with the built-in
low VCC sensing circuit within each Flash device. If the exter-
nal VCC is below 3.8 V (typical), the write function is inhibited.
The fourth type of write protection is a noise filter circuit within
each Flash device. Any pulse of less than 15 ns (typical) on the
WE, CE1 or CE2 inputs will not initiate a program cycle.
The last type of write protection is based on the Software Data
Protection (SDP) scheme of the AT29C010A devices. Each of
the eight devices needs to enable and disable the SDP individu-
ally. Refer to the SDP Algorithm Table for descriptions of en-
able and disable SDP operations.
Card Detection
Each CD (output) pin should be read by the host system to de-
termine if the memory card is properly seated in the socket. CD1
and CD2 are internally tied to the ground. If both bits are not
detected, the system should indicate that the card must be
re-inserted.
CIS Data
The Card Information Structure (CIS) describes the capabilities
and specifications of a card. The CIS of the AT5FC001 can be
written either by the OEM or by Atmel at the attribute memory
space beginning at address 00000H by using a format utility.
The AT5FC001 contains a separate 2 Kbyte EEPROM memory
for the card’s attribute memory space. The attribute is active
when the REG pin is driven low. D0-D7 are active during at-
tribute memory access. D8-D15 should be ignored. Odd order
bytes present invalid data. Refer to the Attribute Memory
Operations table.
6
AT5FC001
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