ADT7470 データシートの表示（PDF） - Analog Devices

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ADT7470

Temperature Sensor Hub and Fan Controller

Analog Devices 

ADT7470

Data Sheet

SERIAL BUS TIMING SPECIFICATIONS

Table 2.

Parameter1, 2, 3, 4, 5

SERIAL BUS TIMING

Clock Frequency, fSCLK

Glitch Immunity, tSW

Bus Free Time, tBUF

Start Setup Time, tSU;STA

Start Hold Time, tHD;STA

SCL Low Time, tLOW

SCL High Time, tHIGH

SCL, SDA Rise Time, tr

SCL, SDA Fall Time, tf

Data Setup Time, tSU;DAT

Detect Clock Low Timeout, tTIMEOUT

Min Typ Max Unit

50

1.3

600

600

1.3

0.6

100

25 28

400

kHz

ns

μs

ns

ns

μs

μs

300

ns

300

ns

ns

31

ms

Test Conditions/Comments

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

See Figure 2

Can be optionally disabled,

via Configuration Register 1

(see Table 6)

1 VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD.

2 All voltages are measured with respect to GND, unless otherwise specified.

3 Typical values are at %A = 25°C and represent the most likely parametric norm.

4 Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V.

5 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.

SCL

tR

tLOW

tHD;STA

tHD;DAT

SDA

tBUF

P

S

tF

tHIGH

tSU;DAT

tHD;STA

tSU;STA

S

Figure 2. Serial Bus Timing Diagram

tSU;STO

P

Rev. E | Page 4 of 40

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