ADT7317 データシートの表示（PDF） - Analog Devices
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ADT7317 Datasheet PDF : 44 Pages
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ADT7316/ADT7317/ADT7318
Parameter1
Min
Typ Max
Unit
DIGITAL OUTPUT
Output High Voltage, VOH
2.4
V
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
0.4
V
1
mA
50
pF
INT/INT Output Saturation Voltage
0.8
V
I2C TIMING CHARACTERISTICS7, 8
Serial Clock Period, t1
2.5
μs
Data In Setup Time to SCL High, t2
50
ns
Data Out Stable After SCL Low, t3
0
ns
SDA Low Setup Time to SCL Low
50
ns
(Start Condition), t4
SDA High Hold Time After SCL High 50
ns
(Stop Condition), t5
SDA and SCL Fall Time, t6
SDA and SCL Rise Time, t6
300
ns
3009
ns
SPI TIMING CHARACTERISTICS10, 11
CS to SCLK Setup Time, t1
0
ns
SCLK High Pulse Width, t2
50
ns
SCLK Low Pulse Width, t3
50
ns
Data Access Time After SCLK Falling
Edge, t412
Data Setup Time Prior to SCLK
20
Rising Edge, t5
Data Hold Time after SCLK Rising 0
Edge, t6
35
ns
ns
ns
CS to SCLK Hold Time, t7
0
ns
CS to DOUT High Impedance, t8
40
ns
POWER REQUIREMENTS
VDD
2.7
VDD Settling Time
IDD (Normal Mode)13
5.5
V
50
ms
3
mA
2.2 3
mA
IDD (Power-Down Mode)
10
μA
10
μA
Power Dissipation
10
mW
33
μW
Conditions/Comments
ISOURCE = ISINK = 200 μA.
IOL = 3 mA.
VOH = 5 V.
IOUT = 4 mA.
Fast-mode I2C. See Figure 4.
See Figure 4.
See Figure 4.
See Figure 4.
See Figure 4.
See Figure 4.
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD , and VIL = GND.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD, and VIL = GND.
VDD = 3.3 V, using normal mode.
VDD = 3.3 V, using shutdown mode.
1 See the Terminology section.
2 DC specifications tested with the outputs unloaded.
3 Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).
4 A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.
5 Guaranteed by design and characterization, but not production tested.
6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD, offset plus
gain error must be positive.
7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate,
but has a negative effect on the EMC behavior of the part.
8 Guaranteed by design. Not tested in production.
9 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
10 Guaranteed by design and characterization, but not production tested.
11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
12 Measured with the load circuit of Figure 5.
13 IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Rev. B | Page 5 of 44
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