ADSP-2195MKCA-160 データシートの表示（PDF） - Analog Devices

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ADSP-2195MKCA-160

DSP Microcomputer

Analog Devices 

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ADSP-2195

For current information contact Analog Devices at 800/262-5643

September 2001

External (Off-Chip) Memory

Each of the ADSP-2195’s off-chip memory spaces has a

separate control register, so applications can configure

unique access parameters for each space. The access param-

eters include read and write wait counts, waitstate

completion mode, I/O clock divide ratio, write hold time

extension, strobe polarity, and data bus width. The core

clock and peripheral clock ratios influence the external

memory access strobe widths. For more information, see

Clock Signals on page 14. The off-chip memory spaces are:

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through

the External Port, which can be configured for 8-bit or

16-bit data widths.

External Memory Space

External memory space consists of four memory banks.

These banks can contain a configurable number of 64K

word pages. At reset, the page boundaries for external

memory have Bank0 containing pages 1−63, Bank1 con-

taining pages 64−127, Bank2 containing pages 128−191,

and Bank3 containing Pages 192−254. The MS3–0

memory bank pins select Banks 3–0, respectively. The

external memory interface decodes the 8 MSBs of the DSP

program address to select one of the four banks. Both the

ADSP-219x core and DMA-capable peripherals can access

the DSP’s external memory space.

I/O Memory Space

The ADSP-2195 supports an additional external memory

called I/O memory space. This space is designed to support

simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data regis-

ters. I/O space supports a total of 256K locations. The first

8K addresses are reserved for on-chip peripherals. The

upper 248K addresses are available for external peripheral

devices. The DSP’s instruction set provides instructions for

accessing I/O space. These instructions use an 18-bit

address that is assembled from an 8-bit I/O page (IOPG)

register and a 10-bit immediate value supplied in the

instruction. Both the ADSP-219x core and a Host (through

the Host Port Interface) can access I/O memory space.

Interrupts

The interrupt controller lets the DSP respond to 17 inter-

rupts with minimum overhead. The controller implements

an interrupt priority scheme as shown in Table 1. Applica-

tions can use the unassigned slots for software and

peripheral interrupts.

Table 1. Interrupt Priorities/Addresses

Interrupt

IMASK/ Vector

IRPTL Address1

Emulator (NMI)—

Highest Priority

NA

NA

Reset (NMI)

0

0x00 0000

Power-Down (NMI)

1

0x00 0020

Loop and PC Stack

2

0x00 0040

Emulation Kernel

3

0x00 0060

User Assigned Interrupt

4

0x00 0080

User Assigned Interrupt

5

0x00 00A0

User Assigned Interrupt

6

0x00 00C0

User Assigned Interrupt

7

0x00 00E0

User Assigned Interrupt

8

0x00 0100

User Assigned Interrupt

9

0x00 0120

User Assigned Interrupt

10

0x00 0140

User Assigned Interrupt

11

0x00 0160

User Assigned Interrupt

12

0x00 0180

User Assigned Interrupt

13

0x00 01A0

User Assigned Interrupt

14

0x00 01C0

User Assigned Interrupt— 15

Lowest Priority

0x00 01E0

1These interrupt vectors start at address 0x10000 when the DSP is in

“no-boot”, run-form-external memory mode.

Boot Memory Space

Boot memory space consists of one off-chip bank with 254

pages. The BMS memory bank pin selects boot memory

space. Both the ADSP-219x core and DMA-capable

peripherals can access the DSP’s off-chip boot memory

space. After reset, the DSP always starts executing instruc-

tions from the on-chip boot ROM. Depending on the boot

configuration, the boot ROM code can start booting the

DSP from boot memory. For more information, see Booting

Modes on page 15.

Table 2 shows the ID and priority at reset of each of the

peripheral interrupts. To assign the peripheral interrupts a

different priority, applications write the new priority to their

corresponding control bits (determined by their ID) in the

Interrupt Priority Control register. The peripheral inter-

rupt’s position in the IMASK and IRPTL register and its

vector address depend on its priority level, as shown in

Table 1. Because the IMASK and IRPTL registers are

limited to 16 bits, any peripheral interrupts assigned a

8

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrA

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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